1. Field of the Invention
The present invention generally relates to a flat panel display device and, more particularly, to a flat panel display device in which both the wiring width of a common power supply line and the panel size may be reduced by allowing the common power supply line (Vdd line) to be constantly curved.
2. Description of the Related Art
FIG. 1A is a schematic plan view of light emitting region and non-light emitting region of an organic electroluminescent (EL) device, and FIG. 1B is a cross-sectional view taken along the line I-I of FIG. 1A for showing a stacked structure of the common power supply line of the organic EL device.
As shown in FIG. 1A, the organic EL device comprises a light emitting region 100 and a non-light emitting region 200, and the non-light emitting region 200 is positioned in a periphery of a panel. A common power supply line 54 is arranged in the non-light emitting region 200 of the periphery of the panel to supply a common voltage to the light emitting region 100.
As shown in FIG. 1B, a buffer layer 15, a gate insulating layer 30, and an interlayer insulating layer 40 may be sequentially stacked. A common power supply line 54 may be arranged on the interlayer insulating layer 40 in the non-light emitting region 200 of the periphery of the panel and formed of the same material as source/drain electrode.
In the related art, a signal line such as a gate line is not formed below the common power supply line 54 in order to prevent an electrical short. Thus the common power supply line 54 is fabricated with a width of about 1.5 mm so as to maintain constant wiring resistance. Consequently the total size of the panel increases.
Furthermore, in the conventional organic EL device, the size of the panel increases due to wiring width of the common power supply line arranged in the light emitting region 100 as well as that of the common power supply line 54 arranged in the non-light emitting region 200 in the periphery of the panel.
FIG. 2A is a plan view for showing a plan structure of the light emitting region of the organic EL device of FIG. 1A, and FIG. 2B is a cross-sectional view taken along the line II-II of FIG. 2A.
As shown in FIG. 2B, the light emitting region of the organic EL device may include A region where a pixel electrode and a driving thin film transistor are formed on a transparent insulating substrate 10, B region where a common power supply line is wired, and C region where a capacitor is formed.
A buffer layer 15 is formed on the insulating substrate 10, and a driving thin film transistor including a semiconductor layer 20 having source/drain regions 21 and 22, and a channel region 23, a gate electrode 31, and source/drain electrodes 51 and 52 connected to the source/drain regions 21 and 22 through contact holes 41 and 42, is formed in a region above the buffer layer 15 in the A region, and a capacitor comprised of a first electrode 32 and a second electrode 53 is formed in the C region.
A gate insulating layer 30 is formed between the semiconductor layer 20, and a gate electrode 31 and a first electrode 32. An interlayer insulating layer 40 is formed between the gate electrode 31 and the first electrode 32, and source/drain electrodes 51, 52 and a second electrode 53. Then a passivation layer 60 is formed.
A pixel electrode 70 is formed as an anode electrode on the passivation layer 60, and is connected to one of the source/drain electrodes 51 and 52, for example, to the drain electrode 52 through the via hole 61, and a planarizing layer 80 having an opening 81 for exposing some portion of the pixel electrode 70 may be formed on the passivation layer 60 including the pixel electrode 70.
An organic light-emitting layer 90 may be formed on the opening 81, and a cathode electrode 95 may be formed on the organic light-emitting layer 90.
As shown in FIG. 2A, the organic EL device comprises a plurality of signal lines, namely, a gate line 35 for applying a scanning signal, a data line 55 for applying a data signal, and a common power supply line 54 for applying a common voltage Vdd to all pixels to provide a reference voltage necessary for driving the driving thin film transistor.
Pixels may be arranged per pixel region defined by these signal lines 35, 54, and 55, wherein each pixel may be comprised of a plurality of thin film transistors connected to those signal lines, one capacitor, and an organic EL device.
In the conventional organic EL device, the gate line 35 and the first electrode 32 of the capacitor may be formed when the gate electrode 31 may be formed, and the data line 55, the power supply line 54, and a second electrode 53 of the capacitor may be formed when the source/drain electrodes 51 and 52 may be formed. In this case, the second electrode 53 of the capacitor and one of the source/drain electrodes 51 and 52 have structures extended from the common power supply line 54. In other words, the common power supply line 54 may be concurrently formed while the source/drain 51 and 52 electrodes are formed.
The common power supply line 54 in the light emitting region 100 may also be stacked in the same manner as the non-light emitting region 200 of the periphery of the panel, which causes the panel size to be increased due to wiring width of the common power supply line 54.